A variety of applications, as for example real-time imaging for missiles, require a cyclic series of sets of repetitive computations to be reliably made at an extremely rapid rate with a minimum of hardware. Existing processors are inherently limited in speed by their need to fetch an instruction from memory, execute it, and store the result, in every operational cycle. Also, known processor chips require external support circuitry such as decoders, buffers, etc., and they require substantial drive power. Furthermore, timing problems and input-output delays make it difficult for conventional processors to do large-scale parallel processing without a large amount of hardware, and testing is difficult.
Prior art in this field includes a processor manufactured by Zoran Corporation of Santa Clara, Calif. which computes a fast Fourier transform (FFT) with n points on a single instruction, but which is not programmable; and U.S. Pat. No. 4,807,183 which shows an interconnection chip with a software-configurable crossbar array but without on-chip computational circuits.